Technical Information of S5L8700X07(SIP)

Pin Assignment

ball Description
-------------------------
A2 - AGND
A3 - P6.4/nSMCS3/RxD1
A4 - AVDD
A5 - P6.0/SMBUSY
A6 - P5.1/ATAPI DA1/-/-/-
A7 - LHPOUT
A8 - P4.3/ATAPI IORDY/-/-/-
A9 - USBXO
A10 - USBXI
A11 - VDDA33C6
A12 - DM
A13 - DP
A14 - P3.1/ATAPI HD9/LCDif D9/-/SMC IO 9
A15 - VDDI6
A16 - LLINEIN
A17 - RLINEIN
B1 - P6.7/SMC ALE
B2 - nARM_ADM
B3 - TEST
B4 - VDDE7
B5 - P5.3/ATAPI CS0/-/-/-
B6 - P5.4/ATAPI CS1/-/-/-
B7 - P5.0/ATAPI DA0/-/-/-
B8 - P4.0/ATAPI CBLID/-/-/-
B9 - P3.7/ATAPI HD15/LCDif D15/-/SMC IO 15
B10 - HPVDD
B11 - ADCLRC
B12 - VSSA33T4
B13 - P2.6/ATAPI HD6/LCDif D6/SDC D6/SMC IO 6
B14 - P3.0/ATAPI HD8/LCDif D8/SDC D0/SMC IO 8
B15 - P2.4/ATAPI HD4/LCDif D4/SDC D4/SMC IO 4
B16 - P2.2/ATAPI HD2/LCDif D2/-/SMC IO 2
B17 - P2.1/ATAPI HD1/LCDif D1/-/SMC IO 1
B18 - P2.0/ATAPI HD0/LCDif D0/MSD/SMC IO 0
C1 - nRESET
C2 - P7.0/LCDnRST/VCLK
C3 - P6.6/MS clock
C4 - P6.1/nSMCS0
C5 - P6.3/nSMCS2/TxD1
C6 - P5.2/ATAPI DA2/-/-/-
C7 - RHPOUT
C8 - P4.5/ATAPI DIOR/LCDif nRD/-/SMC nRD
C9 - P3.4/ATAPI HD12/LCDif D12/-/SMC IO 12
C10 - P3.5/ATAPI HD13/LCDif D13/SDC WP/SMC IO 13
C11 - VDDA33T5
C12 - ADCDAT
C13 - VDDI7
C14 - VDDE6
C15 - P2.5/ATAPI HD5/LCDif D5/SDC D5/SMC IO 5
C16 - MDB0/VD0/LCDif D0
C17 - MDB2/VD2/LCDif D2
C18 - MDB1/VD1/LCDif D1
D1 - nTRST_DBG
D2 - P7.1/LCDnCS
D3 - P6.5/SDCLK,MMCLK
D6 - P6.2/nSMCS1
D7 - P4.4/ATAPI DIOW/LCDif nWR/MS BS/SMC nWR
D8 - P3.6/ATAPI HD14/LCDif D14/-/SMC IO 14
D9 - VSSA33C7
D10 - VSSA33T3
D11 - VDDA33T1
D12 - VSSE6
D13 - P2.3/ATAPI HD3/LCDif D3/-/SMC IO 3
D16 - MDB3/VD3/LCDif D3
D17 - MDB4/VD4/LCDif D4
D18 - MDB7/VD7/LCDif D7
E1 - TDI_DBG
E2 - P7.2/IISMCK
E3 - P7.3/IISWS
E16 - MDB11/VD11/LCDif D11
E17 - MDB5/VD5/LCDif D5
E18 - MDB15/VD15/LCDif D15
F1 - XI
F2 - P7.5/IISD_OUT
F3 - TCK_DBG
F4 - P7.4/IISBCLK
F7 - P4.7/ATAPI INTRQ/-/-/-
F8 - ANALOGTEST
F9 - P3.3/ATAPI HD11/LCDif D11/SDC D3/SMC IO 11
F10 - REXT
F11 - VSSA33T2
F12 - VSSI7
F15 - MDB14/VD14/LCDif D14
F16 - MDB10/VD10/LCDif D10
F17 - MDB6/VD6/LCDif D6
F18 - MDB13/VD13/LCDif D13
G1 - XO
G2 - P7.6/IISD_IN
G3 - TDO_DBG
G4 - P7.7/SPDIFOut
G6 - BOOT_MODE
G7 - VSSE7
G8 - P4.2/ATAPI DMARQ/-/-/-
G9 - P4.6/ATAPI RESET/-/-/SMC nWP
G10 - P4.1/ATAPI DMACK/LCDif REG/-/SMC CLE
G11 - P3.2/ATAPI HD10/LCDif D10/SDC D2/SMC IO 10
G12 - VSSE9
G13 - P2.7/ATAPI HD7/LCDif D7/SDC D7/SMC IO 7
G15 - DQM1
G16 - MDB8/VD8/LCDif D8
G17 - MDB12/VD12/LCDif D12
G18 - DQM0
H1 - LOUT
H2 - HPGND
H3 - P0.0/TAOUT/nSSI
H4 - P0.2/TCOUT/MOSI
H6 - TMS_DBG
H7 - VDDE0
H8 - VSSI1
H11 - VSSE5
H12 - VSSI0
H13 - VDDE9
H15 - VDDE5
H16 - MDB9/VD9/LCDif D9
H17 - VDDI5
H18 - NORVSS
J1 - ROUT
J2 - P0.7/RxD
J3 - P0.4/TEXTCLK
J4 - P0.1/TBOUT/SPICLK
J6 - VDDI0
J7 - VSSE0
J12 - VREF
J13 - nRAS
J15 - nDWE
J16 - DCLKN
J17 - DBVDD
J18 - DCKE
K1 - P1.1/Ext Int1
K2 - P0.5/TCAP
K3 - P10.0/IICCLK
K4 - P1.0/Ext Int0
K6 - P0.3/TDOUT/MISO
K7 - P0.6/TxD
K8 - VDDI1
K12 - VDDE8
K13 - nCAS
K15 - nDCS1
K16 - DCLK
K17 - DGND
K18 - XTO
L1 - VMID
L2 - P1.2/Ext Int2
L3 - P1.6/Ext Int6
L4 - P1.4/Ext Int4
L6 - P1.3/Ext Int3
L7 - P1.5/Ext Int5
L8 - VSSI2
L11 - VSSE8
L12 - VSSE4
L13 - nDCS0
L15 - DQS0
L16 - DQS1
L17 - DCVDD
L18 - nDCS2
M1 - P1.7/Ext Int7/ExtCLK CLCD
M2 - MICIN
M3 - P10.1/IICDAT
M4 - VDDE1
M6 - VSSE1
M7 - VSSI4
M8 - LCDif D4/VD4/SDB4
M9 - LCDif D7/VD7/SDB7
M10 - VSSI3
M11 - VDDI3
M12 - MDA10/LCDif REG
M13 - MDA3/VD19
M15 - DCLK2
M16 - MDA2/VD18
M17 - MDA1/VD17
M18 - NORVCC
N1 - MICBIAS
N2 - VBUS
N3 - P5.7/SDC D1(Int)
N4 - P5.5
N7 - P5.6/SDC CMD
N8 - VDDI1
N9 - VSSI5
N10 - LCDif V3/VD3/SDB3
N11 - PLL0_VDDA
N12 - PLL0_VSSBBA
N15 - MDAB1
N16 - MDAB0
N17 - NORVSS
N18 - MDA0/VD16
P1 - nSWE
P2 - nSOE
P3 - VD19/SDA15
P16 - VDDI4
P17 - VDDE4
P18 - MODE
R1 - nSCS0
R2 - nSCS1
R3 - nSCS2
R6 - LCDif REG/SDA22
R7 - VSSE2
R8 - LCDif D1/VD1/SDB1
R9 - LCDif D6/VD6/SDB6
R10 - LCDif D9/VD9/SDB9
R11 - LCDif D14/VD14/SDB14
R12 - VDDE3
R13 - MDA8/LCDif nWR
R16 - MDA12
R17 - MDA11
R18 - CSB
T1 - SDA1
T2 - SDA2
T3 - SDA5
T4 - VSYNC/SDA10
T5 - VD20/SDA16
T6 - SDA0
T7 - VD22/SDA18
T8 - LCDif nWR/SDA20
T9 - LCDIf D2/VD2/SDB2
T10 - LCDif D11/VD11/SDB11
T11 - VSSI6
T12 - VSSE3
T13 - PLL_VSSD
T14 - MDA6/VD22
T15 - PLL1_VSSBBA
T16 - ADC_VCC
T17 - MDA7/VD23
T18 - MDA4/VD20
U1 - SDA3
U2 - SDA4
U3 - SDA6
U4 - VD17/SDA13
U5 - VD16/SDA12
U6 - VD18/SDA14
U7 - VD21/SDA17
U8 - VDDI2
U9 - VDDE2
U10 - LCDif D8/VD8/SDB8
U11 - LCDif D12/VD12/SDB12
U12 - LCDif D15/VD15/SDB15
U13 - PLL1_VDDA
U14 - PLL_VDDD
U15 - PLL_VBBD
U16 - ADC_VSSA
U17 - MDA9/LCDif nRD
U18 - MDA5/VD21
V2 - SDA7
V3 - HSYNC/SDA11
V4 - VCLK/SDA8
V5 - VDEN/SDA9
V6 - VD23/SDA19
V7 - LCDif nRD/SDA21
V8 - LCDif D0/VD0/SDB0
V9 - LCDif D5/VD5/SDB5
V10 - LCDif D10/VD10/SDB10
V11 - LCDif D13/DV13/SDB13
V12 - CP0
V13 - CP1
V14 - ADC3
V15 - ADC0
V16 - ADC1
V17 - ADC2

I just stumbled onto:

http://web.interware.hu/rudas/dbalatoni/S5L840F.pdf

Many of the registers are at the same addresses as the ones you found for the S5L8700. Did you use this one as a reference? If not I think it could be useful.

The Waltz is a very close member to the Blues SIP in the Samsung S5xxxxx family, they have common DNA, so it's a good reference in this way, but the function blocks and register maps are not identical, we can gather info from the datasheets of more recent mcu such as S3C6400.

I'm be back after the Easter, wish you all guys have a good holiday.

Hi kgb2008, can you take a look at the header file we made for the S5L8700? Maybe you can spot some mistakes. There are 2 'FIXME's in there. Maybe those registers. From the datasheet I guess those should in fact be multiple registers (which we could number) but I'm not sure.

http://130.89.160.166/rockbox/s5l8700.h

markun: It's fine, just a few of mistakes,

1) The name of UART0 and UART1 registers is duplicated.
2) The base address of CLCD block should be 0x39200000.

BTW, the code will be more compact & efficient if we also declare the SFRS blocks as structures.

Originally Posted by kgb2008

1) The name of UART0 and UART1 registers is duplicated.
2) The base address of CLCD block should be 0x39200000.

ok, I fixed those problems. Also, it turned out the version on my webserver was not the latest version I had made, so there might be a few more changes now.

I noticed that sometimes the register names at the start of the chapters don't always match with the names used in the detailed register descriptions.

BTW, the code will be more compact & efficient if we also declare the SFRS blocks as structures.

ok, we can do that when/if we to use the CalmADM.

Also, as soon as I've changed the rockbox source enough that it will give us a .dfu file with some minimal testcode inside I will commit it so other people can also work on it. Hopefully I will have a bit more time this week than I had in the last two.

this sounds promising, any idea when the first (test-)build of rockbox could be available for testing?

Hello

i work on the ipod nano generation 2, which has the S5L8701- B05
I search bits of doc on it. the ball layout is like following : http://f4eru.free.fr/SOC FBGA pins.pdf
Does someone have pinout info ?